The fabrication of semiconductor devices, such as logic and memory devices, typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. As semiconductor device size become smaller and smaller, it becomes critical to develop enhanced monitoring and review devices and procedures. Overlay measurements may currently be performed using an optical measurement system on overlay targets placed in the scribe line of a die of a semiconductor device following an “after development inspection” (ADI) step. This approach is typically fast and in cases where results are out of specification, the sample (e.g., semiconductor wafer) may be reworked. As device feature size continues to scale down and multi-patterning processes become more widely used in integrated circuits (IC) chip manufacturing, overlay control become much tighter. In addition, optical overlay measurement on scribe line at the ADI step is no longer sufficient for overlay control of real IC device at an “after etch inspection” (AEI) step. As a result, the use of scanning electron microscope (SEM) overlay measurements at the AEI step in device patterns becomes necessary.
Currently, SEM overlay targets are designed with a line-space array pattern, which must be measured at the border of a first mask and a second mask so that the patterns from the two layers can be identified. Such an approach is limited in that it can only be performed at the array boarder. The approach may be formed on either test patterns or device patterns, which typically are patterned differently from the array center due to the loading effect, which has a negative impact on measurement results. Therefore, a system and method that cures the shortcomings of previous multi-pattern measurement approaches is desired.